Pipeline
overlapping execution / Parallelism improves performance




if -> instruction fetch
id -> decode instruction and (read) register
ex -> execution (operation) and calculate address
mem -> (access memory operand)
wb -> write result back to register




hazards
1. Structure
require separate instruction/data memories or caches
2. Data
a.stall b.bypassing/forwarding c.scheduling
3. Control
a.stall b.prediction c.reduce branch time


SRAM / Cost Highest / Speed Fastest
DRAM / Cost Higher  / Speed Faster
Magnetic Disk / Cost the less / Speed slowest


cache
1. direct associated 2.set associated 3.fully associated


Write-through -> Updates both upper and lower hierarchy memory
Write-back -> Updates both upper hierarchy memory, and updates lower if needed




compulsory miss -> 一開始啟動時沒寫入資料 肯定會發生的miss情況 (cold start miss
)
capacity miss -> due to finite cache size
conflict miss -> due to not fully associated




virtual memory -> the main memory works as a "cache" of a magnetic disk




bit->byte->word->block->page


register->cache->memory->secondary magnetic disk


RAID 0 - No Redundancy
RAID 1 - Mirroring
RAID 2 - Error Detection and Correction Code
RAID 3 - Bit Parity Bit
RAID 4 - Block Parity Bit
RAID 5 - Distributed Block Parity Bit
RAID 6 - P+Q Redundancy


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